Here, we will review how to make basic components from CMOS.  Our basic building blocks are nFETs and pFETs.  Let's start with the former:


(These figures are from Digital System Deisgn, J. P. Uyemura, unless cited otherwise.)  In all this discussion, G = Gate, S = Source, D = Drain.  It is the value of the voltage between the Gate and the Source, VGS or we sometimes use the opposite polarity VSG, that controls the behavior of a FET. 

Above we see how current flows through an nFET.  When the VGS input is low, the device is off, i.e., it acts like an open circuit.  When VGS is high, the device is on, and acts like a short.  You will have a chance to learn the physics of how it does this in another class.  For now, consider it magic. 

The main point is that this is a voltage-controlled switch.  Just like a light switch can be turned on and off, you can turn this switch on and off by applying a voltage to the VGS input.  To make this point completely clear, we redraw the nFET as a switch model:



Whenever you see a circuit with elements like in Figure 6.5, you can imagine them as in 6.6.  Switches like these are the building blocks of our logic gates.

We could stop at this point and build logic devices just from the switches in Figure 6.6, but we don't.  The reason for this is that nFETs have a strong logic zero but a weak logic 1.  We can see this by considering Figure 6.5 (b).  If we tie the S in the figure to Ground, then the short created by the FET means that the voltage at D is also low.  Since the circuit is a short, nothing we do at D will change that.  So, when G = 1, the output voltage is a strong logic 0.

Therefore, we would like a device that does the opposite: has a strong logic 1 and a weak logic 0.  For this we use the pFET, pictured below:



This acts logically opposite to the nFET, so the diagram differs only in the inverter bubble near G, and the voltage difference is written in the opposite direction.  That is, where we had VGS before, now we have VSG.  So, Figure 6.9 (a) has current flowing from S to D (drawn "upside down" in comparison with the nFET).  When we see the inverter, later, we shall see that the short is to high voltage instead of to ground.  (That is why the pFET is drawn "upside down").  This is a very important point because it is necessary to understand the switch model below:


It really would be better if Figure 6.11 were drawn upside down, and the direction of current flow in 6.11 (a) were reversed.  You can redraw (or imagine) the circuit this way if you prefer.  For the pFET, VSG  = VDD - G , so that Figure 6.9 (a), where  VSG  = VDD, could be rewritten as:

VSG  = VDD - G = VDD - 0   = VDD .  That is, this corresponds to Figure 6.11 (a) where G = 0.  Similarly, for Figure 6.9 (b),

VSG  = VDD - G = VDD - VDD   = 0.   Thus, G in Figure 6.9 (b) is a high voltage, or logic 1, and matches the G = 1 in Figure 6.11 (b).


Now we can look at the CMOS pieces put together in an inverter.  See Figures 6.15 and 6.16 below:



Figure 6.15 shows the inverter, and 6.16 shows it at work.  We are using nFETs and pFETs in a Complementary manner.  In fact, that is the "C" in CMOS.  This way, we get both strong logic 1 and 0 states.  If we leave off the pFET, we have exactly the quasibidirectional device from page 22 of our T.W. Schultz text. 


Complementary use of nFETs and pFETs is also done on more complicated gates.  We can see the building blocks for this in Figures 6.18 and 6.19:

As you can guess from these figures, it is possible to use FETs in series and parallel (Complementary) combinations to make AND and OR gates.  However, NAND and NOR gates are actually simpler.  To see that, consider the NAND gate:


Here, the nFETs are in series and the pFETs are in parallel.  Therefore, if A and B are both 1, then the nFETs are both on, and we have a strong 0 (short to ground).  Otherwise, at least one of the pFETs in parallel will be on, and we will have a strong 1 (short to VDD). 

As you can imagine, a NOR gate would have the nFETs in parallel and the pFETs in series.  Making AND gates and OR gates just involves putting the inverter circuit of Figure 6.15 on the output.  From this, we can build more complicated circuits.

You can easily build any SOP or POS logic device from all NAND gates and all NOR gates, respectively.  (We'll review this in class.)  You can also build sequential logic devices that way as well.  To see this, consider this example:

With an extra inverter, we could make this into a D flip flop, and with minor complications, we could make it clocked, edge triggered, master-slave, etc.  Even simpler is a basic SRAM element:

which is similar to the SR latch in function.  We get to input and read it with the following modifications:

and can combine them into memory arrays as well.

Anything you want to build is a combination of simple sequential logic elements, memory, and combinatorial logic, plus bus lines for communication.  So, your CpE 111 course, in combination with CpE 213, truly bring you "From CMOS to C Code!"